1. Field of the Invention
The present invention relates to a semiconductor device production method and a semiconductor device. Particularly, the invention relates to a semiconductor device having electrodes arranged at a reduced pitch on a semiconductor substrate and to a production method therefor.
2. Description of Related Art
The semiconductor device mounting technology includes so-called flip-chip connection by which a semiconductor chip is directly connected to a wiring board without packaging thereof. The semiconductor chip for the flip-chip connection includes projection electrodes which are provided on a surface of the chip formed with an active layer including a functional device and interconnections. The projection electrodes are respectively bonded to electrode pads provided on the wiring board to establish the flip-chip connection. In this case, the semiconductor chip per se is a semiconductor device.
FIGS. 26(a), 26(b), 26(c) and 26(d) are schematic sectional views for explaining a production method for a conventional semiconductor device having projection electrodes.
An active layer 102 including a functional device and interconnections is formed in one surface of a semiconductor substrate 101, such as a semiconductor wafer, preliminarily planarized, and electrode pads 103 for electrically connecting the functional device in the active layer to an external device are formed at predetermined positions on the active layer 102.
Subsequently, a passivation film 107 is formed on the semiconductor substrate 101 so as to expose the electrode pads 103. Then, a barrier metal layer (UBM: under bump metal) 104 for protection of the electrode pads 103 and the active layer 102 is formed over the surface of the resulting semiconductor substrate 101 on the side of the active layer 102. This state is shown in FIG. 26(a).
In turn, a resist film (photoresist) 105 is formed on the barrier metal layer 104 as having apertures 105a in association with the electrode pads 103 (see FIG. 26(b)). The apertures 105a each have an interior sidewall generally perpendicular to the semiconductor substrate 101.
Thereafter, projection electrodes 106 are respectively formed in the apertures 105a of the resist film 105 by electrolytic plating. At this time, an electric current is applied to a plating liquid via the barrier metal layer 104. Thus, the barrier metal layer 104 serves as a seed layer, whereby a metal such as copper is deposited on the barrier metal layer 104 to form the projection electrodes 106 (see FIG. 26(c)).
In turn, the resist film 105 is removed. Further, the barrier metal layer 104 is removed with portions thereof between the electrode pads 103 and the projection electrodes 106 being left. Thus, the projection electrodes 106 projecting from the semiconductor substrate are provided. This state is shown in FIG. 26(d).
As required, low melting point metal layers 108 are respectively formed on the projection electrodes 106 as covering at least distal end faces of the projection electrodes 106. Where the low melting point metal layers 108 are formed by electroless plating after the removal of the resist film 105, for example, the low melting point metal layers 108 cover the entire exposed surfaces of the projection electrodes 106 as shown in FIG. 27(e). That is, the low melting point metal layers 108 cover the side faces of the projection electrodes 106 as well.
Alternatively, the formation of the projection electrodes 106 by the electrolytic plating is completed with the apertures 105a partly left unfilled, and then the low melting point metal layers 108 are formed by the electrolytic plating before the removal of the resist film 105 and the barrier metal layer 104. In this case, the low melting point metal layers 108 are provided only in the apertures 105a as shown in FIG. 28(f). Thereafter, the resist film 105 is removed, and the barrier metal layer 104 is removed with the portions thereof between the electrode pads 103 and the projection electrodes 106 being left. Thus, the projection electrodes 106 are provided as having the low melting point metal layers 108 formed only on the distal end faces thereof as shown in FIG. 28(g).
Then, the semiconductor substrate 101 is diced to provide a plurality of semiconductor chips (semiconductor devices) each having projection electrodes 106. Where the projection electrodes 106 are respectively formed with the low melting point metal layers 108, the semiconductor device can easily be bonded to electrode pads of a wiring board by melting and solidifying the low melting point metal layers 108. Such a semiconductor device production method is disclosed, for example, in the following literature: Yoshiaki Yamamoto, “Chisso's Wafer Bumping Service”, Densi Zairyo (Electronic Materials and Parts), May, 1995, p. 101-104.
However, the projection electrodes 106 formed by the plating are non-uniform in length (or height as measured from the barrier metal layer 104). The growth rate of the projection electrodes 106 is generally proportional to the amperage of the electric current flowing between the barrier metal layer 104 and the plating liquid. However, the amperage of the electric current flowing between the barrier metal layer 104 and the plating liquid is not uniform throughout the plane of the semiconductor substrate 101 (e.g., between the center and periphery of the semiconductor substrate 101).
If the projection electrodes 106 are non-uniform in length, the distal ends of the projection electrodes 106 are not located within the same plane. When the semiconductor chip formed with the projection electrodes 106 is bonded to the electrode pads and the like formed on the wiring board, some of the projection electrodes 106 having a smaller length cannot properly be brought into contact with the electrode pads of the wiring board. This results in a mechanical bonding failure and an electrical connection failure.
The barrier metal layer 104 serving as a base for the plating has steps due to the presence of the passivation film 107. Therefore, the distal end faces of the projection electrodes 106 each have a recessed center portion as shown in FIGS. 26(c), 26(d), 27(e), 28(f) and 28(g). In such a case, the projection electrodes 106 cannot properly be brought into contact with the electrode pads of the wiring board, resulting in a mechanical bonding failure and an electrical connection failure.
During the plating, the projection electrodes 106 grow as expanding the apertures 105a to deform the resist film 105, whereby the projection electrodes 106 each have a width progressively increased toward the distal end thereof. As a result, the projection electrodes 106 each have an inverted trapezoidal section as shown in FIG. 26(d). Where the adjacent electrode pads 103 are spaced a smaller distance (pitch), the distal ends of the projection electrodes 106 provided on the adjacent electrode pads 103 are located in close relation. Therefore, when the semiconductor device is connected to the wiring board, the adjacent projection electrodes 106 are readily brought into contact with each other thereby to be electrically short-circuited. Therefore, it is impossible to arrange the projection electrodes 106 (electrode pads 103) in closer relation, i.e., to reduce the pitch of the projection electrodes 106.
Since limited kinds of metals are usable for the film formation by the plating, there is a limited choice of materials for the projection electrodes 106.
Where the low melting point metal layers 108 are formed by the electroless plating after the removal of the resist film 105, the low melting point metal layers 108 are formed on not only the distal ends but also the side faces of the projection electrodes 106. Since the semiconductor device for the flip-chip connection is connected to the external device via the distal ends of the projection electrodes 106, portions of the low melting point metal layers 108 except those formed on the distal end faces of the projection electrodes 106 are not contributable to the connection, but may cause a short-circuit between the adjacent projection electrodes 106.
Where the low melting point metal layers 108 are formed by the electrolytic plating, the low melting point metal layers 108 are non-uniform in thickness within the plane of the semiconductor substrate 101, like the projection electrodes 106. Therefore, the distal end faces of the projection electrodes 106 including the low melting point metal layer 108 are not located within the same plane, resulting in a bonding failure.
After the projection electrodes 106 are formed by the electrolytic plating, the barrier metal layer 104 is removed by wet etching. However, it is difficult to control the etching amount at this time. Therefore, portions of the barrier metal layer 104 present between the projection electrodes 106 and the passivation film 107 and between the projection electrodes 106 and the electrode pads 103 may partly be removed (over-etched). This results in reduction of the bonding strength of the projection electrodes 106 to the electrode pads 103. Where the portions of the barrier metal layer 104 between the electrode pads 103 and the projection electrodes 106 are etched, the electrode pads 103 are partly exposed (or uncovered). This leads to corrosion of the electrode pads 103, thereby reducing the reliability of the semiconductor device.